github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-03-27 18:50:03 +00:00
Code Issues Releases Wiki Activity

Fixed simlib entries for $memrd and $memwr

Browse Source
This commit is contained in:
Clifford Wolf
2014-12-30 13:33:29 +01:00
parent 120a8313d9
commit ba43cf5807
1 changed files with 2 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/common/simlib.v
View File

@@ -1449,6 +1449,7 @@ parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter TRANSPARENT = 0;
input CLK;
input [ABITS-1:0] ADDR;
@@ -1473,6 +1474,7 @@ parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter PRIORITY = 0;
input CLK;
input [WIDTH-1:0] EN;