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docs: Note partial support of modports

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Krystine Sherwin
2025-10-14 14:59:32 +13:00
parent 25f2a88770
commit bbceaa6b5e
1 changed files with 4 additions and 1 deletions
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docs/source/using_yosys/verilog.rst
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@@ -370,7 +370,10 @@ from SystemVerilog:
- array literals are currently not supported
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.
ports are inputs or outputs are supported when used with named arguments, but
not positional arguments. i.e. ``driver_mod d0(.intf(intf0),
.in(inputs[0]));`` is supported but ``driver_mod d0(intf0, inputs[0]);`` is
not.
- Assignments within expressions are supported.