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Code Issues Releases Wiki Activity

timinginfo: special-case $specify2 in signorm invariant

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This commit is contained in:
Emil J. Tywoniak
2026-03-26 19:42:33 +01:00
parent d33d048874
commit c06755f1bb
2 changed files with 4 additions and 5 deletions
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2
kernel/rtlil_bufnorm.cc
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@@ -1057,7 +1057,7 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal)
{
bool is_input_port = false;
if (module->sig_norm_index != nullptr) {
if (module->sig_norm_index != nullptr && type != ID($specify2)) {
module->sig_norm_index->sigmap.apply(signal);
auto dir = port_dir(portname);

7
kernel/timinginfo.h
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@@ -106,10 +106,9 @@ struct TimingInfo
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
// TODO disabled check because signorm breaks this assumption
// for (const auto &c : dst.chunks())
// if (!c.wire || !c.wire->port_output)
// log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
for (const auto &c : dst.chunks())
if (!c.wire || !c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);