Missing endmodule

2026-05-02 06:26:59 +00:00 · 2019-11-22 12:37:57 -08:00
parent 0ab1e496dc
commit c761fa49b7
1 changed files with 1 additions and 0 deletions
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -288,3 +288,4 @@ endmodule
 module abc9_test033(input clk, d, output reg q1, q2);
 always @(posedge clk) q1 <= d;
 always @(posedge clk) q2 <= q1;
+endmodule