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Code Issues Releases Wiki Activity

Get wire via SigBit

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This commit is contained in:
Eddie Hung
2019-08-21 13:47:47 -07:00
parent 52fea5b658
commit cab2bd083e
1 changed files with 4 additions and 4 deletions
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8
passes/pmgen/xilinx_srl.pmg
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@@ -11,7 +11,7 @@ endcode
match first
select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
select !first->get_bool_attribute(\keep)
select !port(first, \Q).as_wire()->get_bool_attribute(\keep)
select !port(first, \Q)[0].wire->get_bool_attribute(\keep)
filter !non_first_cells.count(first)
//generate
// SigSpec A = module->addWire(NEW_ID);
@@ -49,13 +49,13 @@ subpattern setup
match first
select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
select !first->get_bool_attribute(\keep)
select !port(first, \Q).as_wire()->get_bool_attribute(\keep)
select !port(first, \Q)[0].wire->get_bool_attribute(\keep)
endmatch
match next
select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
select !next->get_bool_attribute(\keep)
select !port(next, \Q).as_wire()->get_bool_attribute(\keep)
select !port(next, \Q)[0].wire->get_bool_attribute(\keep)
select nusers(port(next, \Q)) == 2
index <IdString> next->type === first->type
index <SigSpec> port(next, \Q) === port(first, \D)
@@ -74,7 +74,7 @@ match next
semioptional
select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
select !next->get_bool_attribute(\keep)
select !port(next, \Q).as_wire()->get_bool_attribute(\keep)
select !port(next, \Q)[0].wire->get_bool_attribute(\keep)
select nusers(port(next, \Q)) == 2
index <IdString> next->type === chain.back()->type
index <SigSpec> port(next, \Q) === port(chain.back(), \D)