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mirror of synced 2026-05-07 08:31:12 +00:00
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Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port

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muxpack: fix wide Y port handling
This commit is contained in:
Emil J
2026-03-31 10:49:39 +00:00
committed by GitHub
parent 240439bdb0 ecaaea8734
commit cede13a742
2 changed files with 21 additions and 3 deletions
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15
passes/opt/muxpack.cc
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@@ -38,6 +38,9 @@ struct ExclusiveDatabase
pool<Cell*> reduce_or;
for (auto cell : module->cells()) {
if (cell->type == ID($eq)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
const_sig = sigmap(cell->getPort(ID::B));
if (!const_sig.is_fully_const()) {
@@ -45,12 +48,15 @@ struct ExclusiveDatabase
continue;
std::swap(nonconst_sig, const_sig);
}
y_port = sigmap(cell->getPort(ID::Y));
y_port = y_sig[0];
}
else if (cell->type == ID($logic_not)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
const_sig = Const(State::S0, GetSize(nonconst_sig));
y_port = sigmap(cell->getPort(ID::Y));
y_port = y_sig[0];
}
else if (cell->type == ID($reduce_or)) {
reduce_or.insert(cell);
@@ -84,7 +90,10 @@ struct ExclusiveDatabase
}
if (nonconst_sig.empty())
continue;
y_port = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (GetSize(y_sig) == 0)
continue;
y_port = y_sig[0];
sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::move(values));
}
}

9
tests/various/muxpack_wide_y.ys Normal file
View File

@@ -0,0 +1,9 @@
# Regression test for issue #5734: muxpack crash when $logic_not / $eq / $reduce_or
# has Y port width > 1 (e.g. boolean result assigned to a wide wire).
read_verilog <<EOT
module top(input b, output [18:0] h);
assign h = ~|b;
endmodule
EOT
proc
muxpack