github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-16 01:51:02 +00:00
Code Issues Releases Wiki Activity

Mention shregmap -tech xilinx is superseded

Browse Source
This commit is contained in:
Eddie Hung
2019-08-23 12:24:25 -07:00
parent 08139aa53a
commit cee30deef5
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
CHANGELOG
View File

@@ -29,7 +29,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Removed "ice40_unlut"
- Improvements in pmgen: slices, choices, define, generate
- Added "xilinx_srl" for Xilinx shift register extraction
- Removed "shregmap -tech xilinx"
- Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
Yosys 0.8 .. Yosys 0.8-dev
--------------------------