xilinx: fix tests
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@@ -6,6 +6,7 @@ proc
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#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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formalff -clk2ff
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sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd macc # Constrain all select calls below inside the top module
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@@ -20,6 +21,7 @@ proc
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#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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formalff -clk2ff
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sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd macc2 # Constrain all select calls below inside the top module
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@@ -35,6 +35,7 @@ design -stash gate
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design -copy-from gold -as gold pmtest_xilinx_srl_pm_fixed
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design -copy-from gate -as gate pmtest_xilinx_srl_pm_fixed
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formalff -clk2ff
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miter -equiv -flatten -make_assert gold gate miter
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sat -set-init-zero -seq 5 -verify -prove-asserts miter
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@@ -51,5 +52,6 @@ design -stash gate
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design -copy-from gold -as gold pmtest_xilinx_srl_pm_variable
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design -copy-from gate -as gate pmtest_xilinx_srl_pm_variable
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formalff -clk2ff
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miter -equiv -flatten -make_assert gold gate miter
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sat -set-init-zero -seq 5 -verify -prove-asserts miter
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