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Remove extraneous synth_xilinx call

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Eddie Hung
2019-12-12 19:00:26 -08:00
parent 01116f0f0a
commit d0ee4cd88f
1 changed files with 0 additions and 2 deletions
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tests/arch/xilinx/lutram.ys
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@@ -62,7 +62,6 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w3r
proc
memory -nomap
synth_xilinx
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
@@ -83,7 +82,6 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w3r -chparam A_WIDTH 6
proc
memory -nomap
synth_xilinx
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full