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Merge pull request #3040 from YosysHQ/micko/split_module_ports

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Split module ports, 20 per line
This commit is contained in:
Claire Xen
2021-10-11 09:56:05 +02:00
committed by GitHub
parent c15b99c0de ff8e999a71
commit d5cc3a1c72
1 changed files with 2 additions and 0 deletions
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2
backends/verilog/verilog_backend.cc
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@@ -2062,6 +2062,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true);
f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
bool keep_running = true;
int cnt = 0;
for (int port_id = 1; keep_running; port_id++) {
keep_running = false;
for (auto wire : module->wires()) {
@@ -2070,6 +2071,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
f << stringf(", ");
f << stringf("%s", id(wire->name).c_str());
keep_running = true;
if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
continue;
}
}