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Add assertion

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This commit is contained in:
Eddie Hung
2019-12-03 19:21:42 -08:00
parent df52bc80d8
commit d66d06b91d
1 changed files with 1 additions and 0 deletions
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passes/techmap/abc9.cc
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@@ -1107,6 +1107,7 @@ struct Abc9Pass : public Pass {
Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
if (abc9_clock_wire == NULL)
log_error("'%s.$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
log_assert(GetSize(abc9_clock_wire) == 1);
SigBit abc9_clock = sigmap(abc9_clock_wire);
auto r = clocks.insert(abc9_clock.wire);
if (r.second) {