Merge pull request #1571 from YosysHQ/eddie/fix_1570

mem_arst.v: do not redeclare ANSI port
2026-02-04 16:03:04 +00:00 · 2019-12-19 12:21:22 -05:00
parent 8b2c9f4518 23fcfd0adb
commit d675f22f4e
1 changed files with 1 additions and 3 deletions
--- a/tests/simple/mem_arst.v
+++ b/tests/simple/mem_arst.v
@@ -7,11 +7,9 @@ module MyMem #(
  input                  Clk_i,
  input  [AddrWidth-1:0] Addr_i,
  input  [DataWidth-1:0] Data_i,
-  output [DataWidth-1:0] Data_o,
+  output reg [DataWidth-1:0] Data_o,
  input                  WR_i);

-  reg [DataWidth-1:0] Data_o;
-
  localparam Size = 2**AddrWidth;

  (* mem2reg *)