Cleaned verilog code from not used defines

2026-02-12 03:07:07 +00:00 · 2019-10-04 08:45:58 +02:00
parent abb5a3a44d
commit d6ef9b1a6b
1 changed files with 0 additions and 6 deletions
--- a/tests/ecp5/shifter.v
+++ b/tests/ecp5/shifter.v
@@ -9,14 +9,8 @@ in

    always @(posedge clk)
 	begin
-`ifndef BUG
 		out    <= out >> 1;
 		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
 	end

 endmodule