github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-25 00:28:44 +00:00
Code Issues Releases Wiki Activity

Merge pull request #1297 from YosysHQ/eddie/fix_1284_again

Browse Source 
extract_fa: Un-inverting AND with an inverted input also inverts input to X{,N}OR
This commit is contained in:
Eddie Hung
2019-08-15 07:49:02 -07:00
committed by GitHub
parent 704686774e 91f6cdfef6
commit d8a2aaa463
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
passes/techmap/extract_fa.cc
View File

@@ -513,13 +513,13 @@ struct ExtractFaWorker
}
if (func2.at(key).count(xor2_func)) {
SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y;
for (auto bit : func2.at(key).at(xor2_func))
assign_new_driver(bit, YY);
}
if (func2.at(key).count(xnor2_func)) {
SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y);
for (auto bit : func2.at(key).at(xnor2_func))
assign_new_driver(bit, YY);
}