test: add test for #2014

tests/various/bug2014.ys

@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module test (
+        input signed [1:0] n,
+        output [3:0] dout
+);
+        assign dout = n + 4'sd 4;
+endmodule
+EOT
+
+alumacc
+select -assert-count 1 t:$alu
+equiv_opt -assert opt -fine