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tests: add design -delete tests

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This commit is contained in:
Eddie Hung 2020-04-14 10:34:23 -07:00
parent a9ec0defb9
commit e8a841467f
2 changed files with 18 additions and 0 deletions
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9
tests/various/design.ys Normal file
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@ -0,0 +1,9 @@
read_verilog <<EOT
module top(input i, output o);
assign o = i;
endmodule
EOT
design -stash foo
design -delete foo
logger -expect error "No saved design 'foo' found!" 1
design -delete foo

9
tests/various/design2.ys Normal file
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@ -0,0 +1,9 @@
read_verilog <<EOT
module top(input i, output o);
assign o = i;
endmodule
EOT
design -stash foo
design -delete foo
logger -expect error "No saved design 'foo' found!" 1
design -load foo