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Fix extremely stupid typo

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Clifford Wolf
2017-02-11 11:09:07 +01:00
parent 63dfdb5d7f
commit eb7b18e897
1 changed files with 1 additions and 1 deletions
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frontends/verific/verific.cc
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@@ -774,7 +774,7 @@ struct VerificImporter
SigBit outsig = net_map.at(out);
log_assert(outsig.wire && GetSize(outsig.wire) == 1);
outsig.wire->attributes["\\init"] == Const(0, 1);
outsig.wire->attributes["\\init"] = Const(0, 1);
module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
continue;