Also add first.Q to chain_bits since variable length

2026-04-26 20:28:22 +00:00 · 2019-08-23 18:14:06 -07:00
parent 70ce3d0670
commit ee9f6e6243
1 changed files with 1 additions and 0 deletions
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -196,6 +196,7 @@ code clk_port en_port
 		en_port = \EN;
 	else log_abort();

+	chain_bits.insert(port(first, \Q)[slice]);
 	chain.emplace_back(first, slice);
 	subpattern(tail);
 finally