@@ -437,7 +437,7 @@ otherwise.
|
||||
\begin{lstlisting}[mathescape,language=Verilog]
|
||||
always @($ClkEdge$ C, $RstEdge$ R)
|
||||
if (R == $RstLvl$)
|
||||
Q <= $RstVa$l;
|
||||
Q <= $RstVal$;
|
||||
else
|
||||
Q <= D;
|
||||
\end{lstlisting}
|
||||
|
||||
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