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Added AIGER back-end to automatic back-end detection

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Clifford Wolf
2016-12-21 10:16:47 +01:00
parent f31e6a7174
commit f144adec58
1 changed files with 2 additions and 0 deletions
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kernel/yosys.cc
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@@ -903,6 +903,8 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig
command = "verilog";
else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
command = "ilang";
else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig")
command = "aiger";
else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif")
command = "blif";
else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif")