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Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dreg

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N. Engelhardt
2023-02-17 18:40:22 +01:00
committed by GitHub
parent 1cfedc90ce fc56978703
commit f30b539cc2
1 changed files with 1 additions and 1 deletions
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techlibs/xilinx/cells_sim.v
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@@ -3614,7 +3614,7 @@ module DSP48E1 (
if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end
else always @* Cr <= C;
if (CREG == 1) initial Dr = 25'b0;
if (DREG == 1) initial Dr = 25'b0;
if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end
else always @* Dr <= D;