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memlib: fix documentation for PORT_<name>_CLK_POL

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Signed-off-by: Leo Moser <leomoser99@gmail.com>
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Leo Moser
2026-05-09 10:28:07 +02:00
parent 1f02343268
commit fb83719745
1 changed files with 1 additions and 1 deletions
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passes/memory/memlib.md
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@@ -310,7 +310,7 @@ The port clock is always provided on the memory cell as `PORT_<name>_CLK` signal
(even if it is also shared). Shared clocks are also provided as `CLK_<shared_name>`
signals.
For `anyedge` clocks, the cell gets a `PORT_<name>_CLKPOL` parameter that is set
For `anyedge` clocks, the cell gets a `PORT_<name>_CLK_POL` parameter that is set
to 1 for `posedge` clocks and 0 for `negedge` clocks. If the clock is shared,
the same information will also be provided as `CLK_<shared_name>_POL` parameter.