github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-12 00:42:47 +00:00
Code Issues Releases Wiki Activity

write_verilog: Skip empty switches

Browse Source
This commit is contained in:
Krystine Sherwin 2026-01-07 13:09:49 +13:00
parent 0ab967b036
commit fcb8695261
No known key found for this signature in database
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
backends/verilog/verilog_backend.cc
View File

@ -2143,6 +2143,9 @@ void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs)
bool dump_proc_switch_ifelse(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw)
{
if (sw->cases.empty())
return true;
for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
if ((*it)->compare.size() == 0) {
break;