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Code Issues Releases Wiki Activity

fix indentation across files

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This commit is contained in:
Stefan Biereigel
2019-05-23 13:42:30 +02:00
parent 075a48d3fa
commit fd003e0e97
4 changed files with 80 additions and 60 deletions
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6
frontends/ast/ast.cc
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@@ -51,7 +51,7 @@ namespace AST_INTERNAL {
std::map<std::string, AstNode*> current_scope;
const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
RTLIL::SigSpec ignoreThisSignalsInInitial;
std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
AstNode *current_always, *current_top_block, *current_block, *current_block_child;
AstModule *current_module;
bool current_always_clocked;
@@ -195,6 +195,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
is_logic = false;
is_signed = false;
is_string = false;
is_wand = false;
is_wor = false;
was_checked = false;
range_valid = false;
range_swapped = false;
@@ -941,7 +943,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
log("--- END OF AST DUMP ---\n");
}
wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>();
wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>();
if (!defer)
{

2
frontends/ast/ast.h
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@@ -327,7 +327,7 @@ namespace AST_INTERNAL
extern std::map<std::string, AST::AstNode*> current_scope;
extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
extern RTLIL::SigSpec ignoreThisSignalsInInitial;
extern std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
extern std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;
extern AST::AstModule *current_module;
extern bool current_always_clocked;

128
frontends/ast/genrtlil.cc
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@@ -166,37 +166,37 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
// helper function for creating RTLIL code for wand/wor declarations
static void wandwor2rtlil(AstNode *that, RTLIL::Wire *output_wire, bool gen_attributes = true)
{
std::string type;
std::string type;
if (that->is_wand) {
type = "$reduce_and";
} else if (that->is_wor) {
type = "$reduce_or";
} else {
log_file_error(that->filename, that->linenum, "Unrecognized wired logic type.\n");
}
if (that->is_wand) {
type = "$reduce_and";
} else if (that->is_wor) {
type = "$reduce_or";
} else {
log_file_error(that->filename, that->linenum, "Unrecognized wired logic type.\n");
}
std::stringstream sstr;
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
if (gen_attributes)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(0);
cell->setPort("\\A", RTLIL::SigSpec());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->setPort("\\Y", output_wire);
wire_logic_map[output_wire] = cell;
wire_logic_map[output_wire] = cell;
}
// helper class for converting AST always nodes to RTLIL processes
@@ -956,12 +956,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->attributes[attr.first] = attr.second->asAttrConst();
}
if (is_wand || is_wor) {
if (wire->width > 1)
log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n");
wandwor2rtlil(this, wire);
}
if (is_wand || is_wor) {
if (wire->width > 1)
log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n");
wandwor2rtlil(this, wire);
}
}
break;
@@ -1493,45 +1492,44 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// add entries to current_module->connections for assignments (outside of always blocks)
case AST_ASSIGN:
{
bool left_had_const = false;
bool left_had_const = false;
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
RTLIL::SigSpec new_left, new_right;
for (int i = 0; i < GetSize(left); i++)
if (left[i].wire) {
std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(left[i].wire);
if (iter == wire_logic_map.end())
{
new_left.append(left[i]);
} else {
RTLIL::Cell *reduce_cell = iter->second;
RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A");
int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int();
log_warning("%d\n", reduce_cell_in.size());
RTLIL::SigSpec new_left, new_right;
for (int i = 0; i < GetSize(left); i++)
if (left[i].wire) {
std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(left[i].wire);
if (iter == wire_logic_map.end())
{
new_left.append(left[i]);
} else {
RTLIL::Cell *reduce_cell = iter->second;
RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A");
int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int();
RTLIL::Wire *new_reduce_input = current_module->addWire(
stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width));
new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
reduce_cell_in.append(new_reduce_input);
reduce_cell->setPort("\\A", reduce_cell_in);
reduce_cell->fixup_parameters();
new_left.append(new_reduce_input);
}
new_right.append(right[i]);
} else {
left_had_const = true;
}
RTLIL::Wire *new_reduce_input = current_module->addWire(
stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width));
new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
reduce_cell_in.append(new_reduce_input);
reduce_cell->setPort("\\A", reduce_cell_in);
reduce_cell->fixup_parameters();
new_left.append(new_reduce_input);
}
new_right.append(right[i]);
} else {
left_had_const = true;
}
left = new_left;
right = new_right;
left = new_left;
right = new_right;
current_module->connect(RTLIL::SigSig(left, right));
if (left_had_const)
log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
" old assignment: %s = %s\n new assignment: %s = %s.\n",
log_signal(left), log_signal(right),
log_signal(new_left), log_signal(new_right));
if (left_had_const)
log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
" old assignment: %s = %s\n new assignment: %s = %s.\n",
log_signal(left), log_signal(right),
log_signal(new_left), log_signal(new_right));
}
break;
@@ -1576,14 +1574,34 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
if (child->type == AST_ARGUMENT) {
RTLIL::SigSpec sig;
if (child->children.size() > 0)
RTLIL::SigSpec new_sig;
if (child->children.size() > 0) {
sig = child->children[0]->genRTLIL();
for (int i = 0; i < GetSize(sig); i++) {
std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(sig[i].wire);
if (iter == wire_logic_map.end()) {
new_sig.append(sig[i]);
} else {
RTLIL::Cell *reduce_cell = iter->second;
RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A");
int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int();
RTLIL::Wire *new_reduce_input = current_module->addWire(
stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width));
new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
reduce_cell_in.append(new_reduce_input);
reduce_cell->setPort("\\A", reduce_cell_in);
reduce_cell->fixup_parameters();
new_sig.append(new_reduce_input);
}
}
}
if (child->str.size() == 0) {
char buf[100];
snprintf(buf, 100, "$%d", ++port_counter);
cell->setPort(buf, sig);
cell->setPort(buf, new_sig);
} else {
cell->setPort(child->str, sig);
cell->setPort(child->str, new_sig);
}
continue;
}

4
frontends/verilog/verilog_parser.y
View File

@@ -486,10 +486,10 @@ wire_type_token:
TOK_WIRE {
} |
TOK_WOR {
astbuf3->is_wor = true;
astbuf3->is_wor = true;
} |
TOK_WAND {
astbuf3->is_wand = true;
astbuf3->is_wand = true;
} |
TOK_REG {
astbuf3->is_reg = true;