YosysHQ.yosys

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Commit Graph

Author	SHA1	Message	Date
Krystine Sherwin	b14a651142	Docs: Mention verilator for linting Link to verilator in the introduction. Include `verilator --lint-only fifo.v` in the example synth doc. Fix linter warnings in fifo.v.	2024-11-05 13:29:45 +13:00
Krystine Sherwin	bc9cccacf2	docs: Move fifo localparams into module def Fix for failing CI.	2024-03-18 10:02:40 +13:00
Krystine Sherwin	742ec78ca3	Switching example synth to fifo Fifo code based on SBY quick start. Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.	2023-12-18 13:19:01 +13:00

Author

SHA1

Message

Date

Krystine Sherwin

b14a651142

Docs: Mention verilator for linting

Link to verilator in the introduction.
Include `verilator --lint-only fifo.v` in the example synth doc.
Fix linter warnings in fifo.v.

2024-11-05 13:29:45 +13:00

Krystine Sherwin

bc9cccacf2

docs: Move fifo localparams into module def

Fix for failing CI.

2024-03-18 10:02:40 +13:00

Krystine Sherwin

742ec78ca3

Switching example synth to fifo

Fifo code based on SBY quick start.
Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.

2023-12-18 13:19:01 +13:00

3 Commits