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Mono Color

• 1f02343268 Merge pull request #5817 from YosysHQ/emil/clockgate-reject-sdffe main Emil J 2026-05-08 18:38:51 +00:00
• db258e6dd9 Merge pull request #5721 from tefantasy/abc-liberty-args nella 2026-05-08 13:41:01 +00:00
• 3f68ee851b Merge branch 'main' into abc-liberty-args nella 2026-05-08 15:08:12 +02:00
• bfc09777e6 Merge pull request #5858 from YosysHQ/krys/check_before_flatten KrystalDelusion 2026-05-08 02:31:03 +00:00
• 3f354eb03b abc: update log for extra read_lib args Tianji Liu 2026-05-08 07:17:29 +08:00
• 10dc0d48b8 Merge branch 'main' into abc-liberty-args nella 2026-05-07 21:20:17 +02:00
• 425d47ad2c clockgate: test $sdffe rejected Emil J. Tywoniak 2026-05-07 16:13:14 +02:00
• 687e5442f2 clockgate: formal liberty tests Emil J. Tywoniak 2026-05-07 16:08:55 +02:00
• f4a10a4808 clockgate: reject $sdffe for correct priority handling Emil J. Tywoniak 2026-04-20 16:52:53 +02:00
• 4e35ed5955 Merge pull request #5827 from cdleary/cdleary/2026-04-21-sv-positional-assignment-unpacked Emil J 2026-05-07 10:55:17 +00:00
• cb6209506e abc: disable scl merge if extra read_lib args provided Tianji Liu 2026-05-07 18:45:35 +08:00
• f8a50e7174 Merge commit 'ab316c14d2c3f950eda7672e5c5507bb5219205a' into abc-liberty-args Tianji Liu 2026-05-07 18:12:49 +08:00
• 9ca77338e9 Generate coverage for tests coverage Miodrag Milanovic 2026-05-07 09:44:42 +02:00
• 3b26a9e45e Docs: Update synth starter for check before flatten Krystine Sherwin 2026-05-07 17:38:30 +12:00
• b04aadfa44 Add LogSink & LogMessage classes for a more robust sink solution. log-sink Sean Luchen 2025-10-03 08:55:07 -07:00
• f6863b9f70 Fix tests/various/logger_cmd_error.sh. Sean Luchen 2025-09-16 08:59:47 -07:00
• 57a6aff194 Logging: Add log stream that only get sent warning+ logs. Sean Luchen 2025-09-15 11:31:52 -07:00
• ab316c14d2 Merge pull request #5844 from YosysHQ/lofty/abc-refactor-5 Lofty 2026-05-06 13:40:15 +00:00
• de1dd3b1c5 add aiger2_zbuf to constids Lofty 2026-05-06 14:03:07 +01:00
• fecea911ff synth_gatemate: add -abc_new option Lofty 2026-04-30 11:35:03 +01:00
• 6997ed28b3 opt_merge: newcelltypes emil/signorm Emil J. Tywoniak 2026-05-06 13:52:25 +02:00
• 77b63be4d2 Remove unstable san test for mac. nella/abc_new_tests nella 2026-05-06 13:44:10 +02:00
• 0641b7a725 Merge pull request #5850 from YosysHQ/nella/synth-check nella 2026-05-06 11:23:40 +00:00
• 54f99add7e opt_merge: factor out hashing code across incremental and parallel Emil J. Tywoniak 2026-05-06 12:58:32 +02:00
• 6bff991e00 opt_expr: replace invert_map with signorm traversal Emil J. Tywoniak 2026-05-06 12:15:31 +02:00
• ef31e84116 Resolve sig bugfix. nella/refactor-hierarchy nella 2026-05-06 12:24:57 +02:00
• 23de03cea9 signorm: add timers Emil J. Tywoniak 2026-05-06 12:14:48 +02:00
• 404be73579 Build signal index. nella 2026-05-06 12:04:19 +02:00
• 54206f617f Fixup sigdir. nella 2026-05-06 11:51:52 +02:00
• a9bb86543e Resolve wire dir WIP. nella 2026-05-06 11:40:55 +02:00
• e0ef8bb9e9 Refactor hierarchy ports. nella 2026-05-06 11:27:58 +02:00
• 54ef1275bd rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction Emil J. Tywoniak 2026-04-21 15:20:26 +02:00
• a52b8d2f91 check: fix memory bug in $connect Emil J. Tywoniak 2026-04-17 11:54:39 +02:00
• 6d37b670c9 memory_bram: create blackboxes Emil J. Tywoniak 2026-04-16 16:58:48 +02:00
• b4b774f06f Revert "intel: register bram celltypes" Emil J. Tywoniak 2026-04-16 15:50:06 +02:00
• 00437b36eb Revert "tests: use memory -bram-register in tests/bram" Emil J. Tywoniak 2026-04-16 15:50:05 +02:00
• 6bb72212d6 Revert "memory: add -bram-register" Emil J. Tywoniak 2026-04-16 15:50:03 +02:00
• a2e6647339 Revert "memory_bram: add -register" Emil J. Tywoniak 2026-04-16 15:50:01 +02:00
• 12e179bc20 intel_alm: loosen tests Emil J. Tywoniak 2026-04-16 11:57:53 +02:00
• ec7375d2cb gowin: loosen tests Emil J. Tywoniak 2026-04-16 11:56:35 +02:00
• b995059cef flatten: disable signorm Emil J. Tywoniak 2026-04-15 17:31:37 +02:00
• df791a5ac4 ecp5: loosen tests Emil J. Tywoniak 2026-04-15 12:01:00 +02:00
• c5ed5163b3 nexus: loosen tests Emil J. Tywoniak 2026-04-15 12:00:49 +02:00
• 7c083ff204 xilinx_dsp: signorm compatibility Emil J. Tywoniak 2026-04-15 11:37:16 +02:00
• 5d069fcb3a pmgen: hold sigmap pointer instead of owning it Emil J. Tywoniak 2026-04-14 18:05:33 +02:00
• e218c25b30 gowin: rebless LUT counts Emil J. Tywoniak 2026-04-09 13:29:42 +02:00
• 4e4700b456 equiv_miter: don't copy $input_port Emil J. Tywoniak 2026-04-09 13:18:16 +02:00
• a3beac73f6 rtlil_bufnorm: more xlog Emil J. Tywoniak 2026-04-09 13:17:49 +02:00
• 25d127f0dc design: properly switch signorm mode when restoring saved designs Emil J. Tywoniak 2026-04-09 13:16:37 +02:00
• a39ab42b99 equiv_make: don't copy $input_port Emil J. Tywoniak 2026-04-08 11:40:19 +02:00
• 441a1f47fb rtlil: fix cloneInto in signorm Emil J. Tywoniak 2026-04-08 11:39:24 +02:00
• 69ff2fb484 rtlil: sigNormalize Module when added to Design in signorm mode Emil J. Tywoniak 2026-04-07 20:05:51 +02:00
• 81617afa95 rtlil_bufnorm: more xlog Emil J. Tywoniak 2026-04-07 19:30:19 +02:00
• a000a7830c intel: register bram celltypes Emil J. Tywoniak 2026-04-02 17:01:32 +02:00
• 16877b61da rtlil_bufnorm: ignore timing info harder Emil J. Tywoniak 2026-04-02 17:01:09 +02:00
• 1052e89772 gowin: replace positional arguments in cells_sim.v with named Emil J. Tywoniak 2026-04-02 13:00:02 +02:00
• b4bb200dec Revert "techmap: call hierarchy on map files to determine port directions" Emil J. Tywoniak 2026-04-02 11:40:33 +02:00
• 0d62ac186c hierarchy: tolerance for apparent recursive instances in techmap files Emil J. Tywoniak 2026-04-01 13:12:41 +02:00
• 38255da162 techmap: call hierarchy on map files to determine port directions Emil J. Tywoniak 2026-04-01 12:46:31 +02:00
• e78a1a7b3d tests: use memory -bram-register in tests/bram Emil J. Tywoniak 2026-03-31 15:00:26 +02:00
• 33e5d9340f memory: add -bram-register Emil J. Tywoniak 2026-03-31 14:59:59 +02:00
• 23523603dc memory_bram: add -register Emil J. Tywoniak 2026-03-31 14:59:10 +02:00
• e3c428b6a9 ffmerge: initvals signorm compatibility fixup Emil J. Tywoniak 2026-03-26 23:53:53 +01:00
• 8e0a0db296 timinginfo: special-case $specify2 in signorm invariant Emil J. Tywoniak 2026-03-26 19:42:33 +01:00
• d1c463d685 opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped Emil J. Tywoniak 2026-03-25 11:50:17 +01:00
• e4d532b886 connect: remove input ports on conflict Emil J. Tywoniak 2026-03-24 22:39:45 +01:00
• 708bc57e79 opt_dff: sigma harder, FfDataSigMapped Emil J. Tywoniak 2026-03-24 11:32:42 +01:00
• 274823041b ff: add FfDataSigMapped Emil J. Tywoniak 2026-03-24 11:32:29 +01:00
• b58952cf2a opt_dff: temporarily disable signorm due to muxtree traversal Emil J. Tywoniak 2026-03-18 12:56:52 +01:00
• 451d8471b7 tests: fix rtlil roundtrip test Emil J. Tywoniak 2026-03-18 00:48:03 +01:00
• a65d8fbcb9 design: fix signorm commit connectivity to design Emil J. Tywoniak 2026-03-18 00:44:20 +01:00
• 992d20071b cxxrtl: ignore $input_port Emil J. Tywoniak 2026-03-17 18:06:07 +01:00
• 80baffb60e flatten: redo signormalization to work around fanout issue Emil J. Tywoniak 2026-03-17 18:04:41 +01:00
• b8f2dfbd5c abstract: fix test signorm Emil J. Tywoniak 2026-03-17 17:39:05 +01:00
• e75523bf61 signorm: disable passes that use rewrite_sigspecs Emil J. Tywoniak 2026-03-17 17:35:57 +01:00
• 66af891caa aiger: ignore $input_port Emil J. Tywoniak 2026-03-17 17:32:56 +01:00
• 99f88aa7e8 check: stitch info about $connect ports together for driver analysis Emil J. Tywoniak 2026-03-17 17:29:23 +01:00
• e8144f16ac signorm: remove $input cells when leaving Emil J. Tywoniak 2026-03-17 16:37:00 +01:00
• d001b407c4 abstract: skip $input_port cells Emil J. Tywoniak 2026-03-17 16:34:41 +01:00
• e7bffe1d75 flatten: skip $input_port cells in template module Emil J. Tywoniak 2026-03-17 16:11:32 +01:00
• 6f0ba0060e signorm: skip const when fixing fanout Emil J. Tywoniak 2026-03-17 11:28:10 +01:00
• e8dd4868c1 signorm: disable in passes that use swap_names Emil J. Tywoniak 2026-03-16 22:45:29 +01:00
• 0c9d373458 opt_expr: fix invert_map Emil J. Tywoniak 2026-03-13 12:18:48 +01:00
• aa52efb96e satgen: support $connect Emil J. Tywoniak 2026-03-12 22:15:34 +01:00
• f481b5e4df rtlil: add dump_sigmap for hacky signorm debugging Emil J. Tywoniak 2026-03-12 22:13:21 +01:00
• 1da5f4dfef techmap: disable signorm more Emil J. Tywoniak 2026-03-12 22:11:06 +01:00
• 9d98604020 techmap: disable signorm Emil J. Tywoniak 2026-03-11 21:30:27 +01:00
• d37e0acc1f opt_hier: disable signorm Emil J. Tywoniak 2026-03-11 21:26:12 +01:00
• 3c1a0d44df timinginfo: disable output wire check due to signorm Emil J. Tywoniak 2026-03-11 21:25:00 +01:00
• bcf42fcec1 rtlil: forbid rewrite_sigspecs in signorm Emil J. Tywoniak 2026-03-11 21:07:06 +01:00
• 6defcfab50 opt_merge_inc: re add initvals deletion Emil J. Tywoniak 2026-03-11 12:35:16 +01:00
• 4a5ff094ba synth_ice40: always read abc9 model to understand port direction Emil J. Tywoniak 2026-03-11 12:25:37 +01:00
• 547a715659 tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-10 14:09:31 +01:00
• 66f2d67f5e tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-10 14:05:37 +01:00
• 0673455daa tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-10 14:02:46 +01:00
• 42a75ffda9 wreduce: fixup initvals after setPort Emil J. Tywoniak 2026-03-10 14:01:57 +01:00
• b0c3f3ea00 ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire Emil J. Tywoniak 2026-03-09 23:38:10 +01:00
• 92f97bd5e7 tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-09 21:21:45 +01:00
• c5839deb3d rtlil: fix zero width SigSpec crash in signorm setPort unsetPort Emil J. Tywoniak 2026-03-09 21:20:23 +01:00
• 57ee22883a bug2920: disable Emil J. Tywoniak 2026-03-09 16:37:30 +01:00