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Mono Color

• 9ec94375bf Update CI scripts for CMake cat/cmake Miodrag Milanovic 2026-05-22 12:31:30 +02:00
• ab2a1968d3 Migrate build system to CMake Catherine 2026-05-12 05:33:04 +00:00
• 849526491a fixup! tests: signorm fix emil/signorm Emil J. Tywoniak 2026-05-22 21:23:38 +02:00
• 54b35be609 tests: signorm fix Emil J. Tywoniak 2026-05-22 21:20:32 +02:00
• 6039446e60 Visual Studio build micko/cmake-ci Miodrag Milanovic 2026-05-22 19:54:19 +02:00
• 72b60b6cef signorm: safer indexing if broken invariant Emil J. Tywoniak 2026-05-22 17:21:40 +02:00
• dcc68e49fb check: check bufnorm too Emil J. Tywoniak 2026-05-22 13:11:24 +02:00
• 4bff2e6340 check: check signorm indices and wires Emil J. Tywoniak 2026-05-22 13:04:37 +02:00
• b9eae3f64b rtlil: publish signorm fanout Emil J. Tywoniak 2026-05-22 13:04:12 +02:00
• 8f62d5c657 opt_merge: newcelltypes Emil J. Tywoniak 2026-05-06 13:52:25 +02:00
• 7d335ed0d9 opt_merge: factor out hashing code across incremental and parallel Emil J. Tywoniak 2026-05-06 12:58:32 +02:00
• 9abee44602 opt_expr: replace invert_map with signorm traversal Emil J. Tywoniak 2026-05-06 12:15:31 +02:00
• 5dce475325 signorm: add timers Emil J. Tywoniak 2026-05-06 12:14:48 +02:00
• 5de8452b57 rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction Emil J. Tywoniak 2026-04-21 15:20:26 +02:00
• 350385f5a2 check: fix memory bug in $connect Emil J. Tywoniak 2026-04-17 11:54:39 +02:00
• 1dc7a69d7f memory_bram: create blackboxes Emil J. Tywoniak 2026-04-16 16:58:48 +02:00
• 19a4c29a0e Revert "intel: register bram celltypes" Emil J. Tywoniak 2026-04-16 15:50:06 +02:00
• 24d0bf19bc Revert "tests: use memory -bram-register in tests/bram" Emil J. Tywoniak 2026-04-16 15:50:05 +02:00
• 8c4ab49955 Revert "memory: add -bram-register" Emil J. Tywoniak 2026-04-16 15:50:03 +02:00
• c64be26334 Revert "memory_bram: add -register" Emil J. Tywoniak 2026-04-16 15:50:01 +02:00
• 116931861d intel_alm: loosen tests Emil J. Tywoniak 2026-04-16 11:57:53 +02:00
• de481b04b8 gowin: loosen tests Emil J. Tywoniak 2026-04-16 11:56:35 +02:00
• 09f55abf1a flatten: disable signorm Emil J. Tywoniak 2026-04-15 17:31:37 +02:00
• bb19205c79 ecp5: loosen tests Emil J. Tywoniak 2026-04-15 12:01:00 +02:00
• 87931fbf7d nexus: loosen tests Emil J. Tywoniak 2026-04-15 12:00:49 +02:00
• 41b3dbbc28 xilinx_dsp: signorm compatibility Emil J. Tywoniak 2026-04-15 11:37:16 +02:00
• 6fd7f5c02d pmgen: hold sigmap pointer instead of owning it Emil J. Tywoniak 2026-04-14 18:05:33 +02:00
• 394be03d57 equiv_miter: don't copy $input_port Emil J. Tywoniak 2026-04-09 13:18:16 +02:00
• e73b828e07 rtlil_bufnorm: more xlog Emil J. Tywoniak 2026-04-09 13:17:49 +02:00
• 451e01d0a4 design: properly switch signorm mode when restoring saved designs Emil J. Tywoniak 2026-04-09 13:16:37 +02:00
• 38fab51fc1 equiv_make: don't copy $input_port Emil J. Tywoniak 2026-04-08 11:40:19 +02:00
• 7905df89f3 rtlil: fix cloneInto in signorm Emil J. Tywoniak 2026-04-08 11:39:24 +02:00
• 754709aa01 rtlil: sigNormalize Module when added to Design in signorm mode Emil J. Tywoniak 2026-04-07 20:05:51 +02:00
• 5355a1739e rtlil_bufnorm: more xlog Emil J. Tywoniak 2026-04-07 19:30:19 +02:00
• 9717a558cc intel: register bram celltypes Emil J. Tywoniak 2026-04-02 17:01:32 +02:00
• d7b6f1c095 rtlil_bufnorm: ignore timing info harder Emil J. Tywoniak 2026-04-02 17:01:09 +02:00
• 14eaedace4 gowin: replace positional arguments in cells_sim.v with named Emil J. Tywoniak 2026-04-02 13:00:02 +02:00
• a93faf811a Revert "techmap: call hierarchy on map files to determine port directions" Emil J. Tywoniak 2026-04-02 11:40:33 +02:00
• 81b99d83f5 hierarchy: tolerance for apparent recursive instances in techmap files Emil J. Tywoniak 2026-04-01 13:12:41 +02:00
• 0eb215dd97 techmap: call hierarchy on map files to determine port directions Emil J. Tywoniak 2026-04-01 12:46:31 +02:00
• b7c9c8eea6 tests: use memory -bram-register in tests/bram Emil J. Tywoniak 2026-03-31 15:00:26 +02:00
• 67de0c8c9e memory: add -bram-register Emil J. Tywoniak 2026-03-31 14:59:59 +02:00
• 88aa5f190b memory_bram: add -register Emil J. Tywoniak 2026-03-31 14:59:10 +02:00
• 5e313a19a0 ffmerge: initvals signorm compatibility fixup Emil J. Tywoniak 2026-03-26 23:53:53 +01:00
• eb6dd47bd6 timinginfo: special-case $specify2 in signorm invariant Emil J. Tywoniak 2026-03-26 19:42:33 +01:00
• 5bfb631085 opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped Emil J. Tywoniak 2026-03-25 11:50:17 +01:00
• bd8738de15 connect: remove input ports on conflict Emil J. Tywoniak 2026-03-24 22:39:45 +01:00
• aecc173f83 opt_dff: sigma harder, FfDataSigMapped Emil J. Tywoniak 2026-03-24 11:32:42 +01:00
• 7382be6962 ff: add FfDataSigMapped Emil J. Tywoniak 2026-03-24 11:32:29 +01:00
• be7beaf91a opt_dff: temporarily disable signorm due to muxtree traversal Emil J. Tywoniak 2026-03-18 12:56:52 +01:00
• 95eae1aa6d tests: fix rtlil roundtrip test Emil J. Tywoniak 2026-03-18 00:48:03 +01:00
• 21bed1a411 design: fix signorm commit connectivity to design Emil J. Tywoniak 2026-03-18 00:44:20 +01:00
• 6c2a90affc cxxrtl: ignore $input_port Emil J. Tywoniak 2026-03-17 18:06:07 +01:00
• faa1a1065c flatten: redo signormalization to work around fanout issue Emil J. Tywoniak 2026-03-17 18:04:41 +01:00
• bd437f207f abstract: fix test signorm Emil J. Tywoniak 2026-03-17 17:39:05 +01:00
• 4f665d6efc signorm: disable passes that use rewrite_sigspecs Emil J. Tywoniak 2026-03-17 17:35:57 +01:00
• 6447a39c0c aiger: ignore $input_port Emil J. Tywoniak 2026-03-17 17:32:56 +01:00
• 8267dee75a check: stitch info about $connect ports together for driver analysis Emil J. Tywoniak 2026-03-17 17:29:23 +01:00
• b42136aa8c signorm: remove $input cells when leaving Emil J. Tywoniak 2026-03-17 16:37:00 +01:00
• 5c5df513d1 abstract: skip $input_port cells Emil J. Tywoniak 2026-03-17 16:34:41 +01:00
• dad6277a25 flatten: skip $input_port cells in template module Emil J. Tywoniak 2026-03-17 16:11:32 +01:00
• d541def612 signorm: skip const when fixing fanout Emil J. Tywoniak 2026-03-17 11:28:10 +01:00
• 68bb5c6b94 signorm: disable in passes that use swap_names Emil J. Tywoniak 2026-03-16 22:45:29 +01:00
• 4d2a6f2b7a opt_expr: fix invert_map Emil J. Tywoniak 2026-03-13 12:18:48 +01:00
• 422a505435 satgen: support $connect Emil J. Tywoniak 2026-03-12 22:15:34 +01:00
• fb03a34277 rtlil: add dump_sigmap for hacky signorm debugging Emil J. Tywoniak 2026-03-12 22:13:21 +01:00
• b859080ef2 techmap: disable signorm more Emil J. Tywoniak 2026-03-12 22:11:06 +01:00
• 6575e7f1df techmap: disable signorm Emil J. Tywoniak 2026-03-11 21:30:27 +01:00
• 2f7d0913fc opt_hier: disable signorm Emil J. Tywoniak 2026-03-11 21:26:12 +01:00
• 6b06869242 timinginfo: disable output wire check due to signorm Emil J. Tywoniak 2026-03-11 21:25:00 +01:00
• 6d08c53429 rtlil: forbid rewrite_sigspecs in signorm Emil J. Tywoniak 2026-03-11 21:07:06 +01:00
• bb2d6f0e2a opt_merge_inc: re add initvals deletion Emil J. Tywoniak 2026-03-11 12:35:16 +01:00
• 07628a4042 synth_ice40: always read abc9 model to understand port direction Emil J. Tywoniak 2026-03-11 12:25:37 +01:00
• 5b6b11dd44 tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-10 14:09:31 +01:00
• 80a440ed2d tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-10 14:05:37 +01:00
• 69c9f3e619 tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-10 14:02:46 +01:00
• 9d86a6636c wreduce: fixup initvals after setPort Emil J. Tywoniak 2026-03-10 14:01:57 +01:00
• e5266d0fbc ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire Emil J. Tywoniak 2026-03-09 23:38:10 +01:00
• 3dc45005f2 tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-09 21:21:45 +01:00
• af48c1cdfb rtlil: fix zero width SigSpec crash in signorm setPort unsetPort Emil J. Tywoniak 2026-03-09 21:20:23 +01:00
• 80ca3174ea bug2920: disable Emil J. Tywoniak 2026-03-09 16:37:30 +01:00
• e6515cfd93 rtlil_bufnorm: fix cell deletion deferral bug Emil J. Tywoniak 2026-03-07 01:10:04 +01:00
• 28013eccbc tests: adjust to input_port and init behavior (sketchy) Emil J. Tywoniak 2026-03-07 01:08:57 +01:00
• dcc4cbea2f check: don't fail on $input_port Emil J. Tywoniak 2026-03-07 00:42:01 +01:00
• 8c4816c802 mem: fix signorm cell type morph Emil J. Tywoniak 2026-03-07 00:41:24 +01:00
• 423c8be71b WIP half broken snapshot Jannis Harder 2025-10-06 14:39:25 +02:00
• 30505c2cd6 WIP remove dead code Jannis Harder 2025-10-04 14:40:08 +02:00
• ba6083da16 Update CI scripts for CMake Miodrag Milanovic 2026-05-22 12:31:30 +02:00
• cad5353a2a Migrate build system to CMake Catherine 2026-05-12 05:33:04 +00:00
• cf75a6ef45 verific: Fix upto ranges krys/verific_memsize Krystine Sherwin 2026-05-21 09:46:56 +12:00
• 04a1611346 Tests. nella/opt_dff_elim_improvements nella 2026-05-20 15:58:27 +02:00
• bbec8d2902 Gate behind flag. nella 2026-05-20 15:51:04 +02:00
• c6bf13bb94 Implement worklist and SAT counterexample splitting. nella 2026-05-13 10:49:12 +02:00
• d85e3f10de Add tests. nella 2026-04-29 15:55:45 +02:00
• f69a5fc077 Elim equiv bits. nella 2026-04-29 11:21:26 +02:00
• 33a2a3a4fd wip lofty/abc9-refactor-5 Lofty 2026-05-20 14:30:09 +01:00
• b17792c451 Arith tree - parallel prefix. nella/arith_tree_improvements nella 2026-05-20 14:10:08 +02:00
• 9d0cdb8551 Merge pull request #5901 from YosysHQ/test_cleanup main Miodrag Milanović 2026-05-20 10:55:28 +00:00
• a0cbe1a334 verific: Fix non-contiguous memory flattening Krystine Sherwin 2026-05-20 15:18:48 +12:00
• a7c8651b76 Add check_mem command Krystine Sherwin 2026-05-20 15:02:30 +12:00