github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-01 22:17:38 +00:00
Code Issues Releases Wiki Activity
5,948 Commits 134 Branches 66 Tags
02ba85b13302f0d20f6b51cc7fdff2fb953421df
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00