github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-22 05:13:43 +00:00
Code Issues Releases Wiki Activity
4,326 Commits 145 Branches 67 Tags
03cf1532a70d705ada69dcb8ae79ae405a86b7da
Commit Graph

1 Commits

Author SHA1 Message Date
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00