github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-30 21:51:59 +00:00
Code Issues Releases Wiki Activity
15,232 Commits 117 Branches 63 Tags
059228dd4e11b151df2ccb11d4e48e07abf33e8e
Commit Graph

2 Commits

Author SHA1 Message Date
Miodrag Milanovic
acb341745d Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
whitequark
9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00