github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-09 01:50:59 +00:00
Code Issues Releases Wiki Activity
6,320 Commits 119 Branches 64 Tags
0917a5cf720e76a85cd2fa4d8cd3cf9434bdee8f
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00