github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-29 21:28:23 +00:00
Code Issues Releases Wiki Activity
11,648 Commits 133 Branches 66 Tags
0d2377c8a6face25a83f15929e02ce62d99da005
Commit Graph

1 Commits

Author SHA1 Message Date
Maciej Kurc
1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:53:43 +02:00