github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-21 15:07:30 +00:00
Code Issues Releases Wiki Activity
6,209 Commits 121 Branches 64 Tags
0f5bddcd792ed2da2b9a3eb12e775537f394e771
Commit Graph

1 Commits

Author SHA1 Message Date
Maciej Kurc
1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:53:43 +02:00