github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-31 14:12:20 +00:00
Code Issues Releases Wiki Activity
8,041 Commits 117 Branches 63 Tags
19bc429482418aa42861ca0f195d86bc9577e320
Commit Graph

1 Commits

Author SHA1 Message Date
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00