github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-24 16:19:05 +00:00
Code Issues Releases Wiki Activity
526 Commits 120 Branches 64 Tags
1de12e1efc9d346d4c1847ddf9a85c38e9b503ee
Commit Graph

1 Commits

Author SHA1 Message Date
Clifford Wolf
00a6c1d9a5 Major redesign of expr width/sign detecion (verilog/ast frontend) 2013-07-09 14:31:57 +02:00