github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-10 18:39:50 +00:00
Code Issues Releases Wiki Activity
10,772 Commits 120 Branches 64 Tags
1eae6025e7dccc021dcd2a6d658dae40ab02ef9e
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00