Lofty
2859eade0a
analogdevices: update T40LP timings
2026-01-22 18:32:36 +00:00
Lofty
7fd066031f
analogdevices: update T16FFC timings
2026-01-22 18:32:36 +00:00
Lofty
7989eb6030
synth_analogdevices: update timing model and tests
2026-01-22 18:32:36 +00:00
Lofty
b2de70d1d8
analogdevices: double LUT RAM cost
2026-01-22 18:32:36 +00:00
Lofty
f1fd79d1ae
analogdevices: ignore $assert cells
2026-01-22 18:32:36 +00:00
Krystine Sherwin
62beef7340
analogdevices: Fixing up bram
...
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
2026-01-22 18:32:36 +00:00
Krystine Sherwin
be419a2c15
analogdevices: Add BRAM options
...
Enable `-force-params`, and tidy up lutram mapping too.
2026-01-22 18:32:36 +00:00
Lofty
13dea19b06
analogdevices: LUT RAM only on positive edge
2026-01-22 18:32:36 +00:00
Lofty
d263a1f2e7
analogdevices: DSP tweaks
2026-01-22 18:32:36 +00:00
Lofty
c0a894497b
analogdevices: DSP inference
2026-01-22 18:32:36 +00:00
Lofty
de1231c827
analogdevices: remove cells_xtra
2026-01-22 18:32:36 +00:00
Lofty
265436f7a1
analogdevices: timings for t40lp
2026-01-22 18:32:36 +00:00
Lofty
96cf404eb6
analogdevices: use single tech param
2026-01-22 18:32:36 +00:00
Lofty
cf96908545
analogdevices: expreso does not care about clock buffers
2026-01-22 18:32:36 +00:00
Lofty
042374198a
analogdevices: prepare for t40lp timings
2026-01-22 18:32:36 +00:00
Krystine Sherwin
793376fef1
analogdevices: Adding RBRAM2 and -tech
2026-01-22 18:32:36 +00:00
Krystine Sherwin
6df69160b8
analogdevices: (some) Native BRAM
...
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
2026-01-22 18:32:36 +00:00
Krystine Sherwin
ce839d4880
analogdevices: Native LUTRAM primitives
2026-01-22 18:32:36 +00:00
Lofty
32d1025659
analogdevices: LUTRAM config
2026-01-22 18:32:36 +00:00
Lofty
529c7a092f
analogdevices: update timing model
2026-01-22 18:32:36 +00:00
Lofty
c3bd8d0949
analogdevices: user retargeting
2026-01-22 18:32:36 +00:00
Lofty
35b1bf9aba
analogdevices: more housekeeping
2026-01-22 18:32:36 +00:00
Lofty
b0ba89ec5b
analogdevices: remove some extra cells!
2026-01-22 18:32:36 +00:00
Lofty
8ab390f8f0
test suite
2026-01-22 18:32:36 +00:00
Lofty
1b386711f1
synth_analogdevices: remove scopeinfo cells
2026-01-22 18:32:36 +00:00
Lofty
261c41b581
Create synth_analogdevices
2026-01-22 18:32:36 +00:00
YRabbit
8a78f2f7c5
Gowin. Fix style.
...
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2026-01-05 20:07:31 +10:00
YRabbit
ea90f54783
Gowin. Implement byte enable.
...
Enable write port with byte enables for BSRAM primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2026-01-03 17:42:49 +10:00
nataliakokoromyti
e289e4c893
add ID::src to allowlist instead
2025-12-17 01:31:32 -08:00
nataliakokoromyti
cf8be2bae7
Update ice40_wrapcarry.cc
2025-12-16 09:33:47 -08:00
Emil J. Tywoniak
1edc32dcd0
opensta, sdc_expand: mark as experimental
2025-11-19 15:31:17 +01:00
Emil J. Tywoniak
85d2702ef6
opensta, sdc_expand: fix help
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
411fc149df
opensta: refactor default command
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
a5b6c3cc19
opensta, sdc_expand: more scratchpad
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
6846168db3
opensta: opensta.exe scratchpad variable
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
5acb77cab1
sdc_expand, opensta: typos
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
7bc88d5c40
sdc_expand: cleanup
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
793594bd59
sdc_expand: log header
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
7bed6ec658
opensta: quiet blackbox warning
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
0c4105d72c
opensta: quiet net width mismatch warning
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
bbf1e4bca2
sdc_expand, opensta: start
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
f47540b950
techlibs: remove cells.lib
2025-11-14 15:40:14 +01:00
Emil J. Tywoniak
f2263642a4
xilinx: fix IdString memory leak
2025-11-13 14:10:52 +01:00
Emil J. Tywoniak
a915143768
ice40: fix IdString memory leak
2025-11-13 14:10:52 +01:00
Emil J. Tywoniak
bc3fc21248
microchip: fix IdString memory leak
2025-11-13 14:10:52 +01:00
KrystalDelusion
39fab4a07f
Makefile: Add gatemate genfiles
...
Allows files to be cleaned with `make clean`, without which it breaks out-of-tree builds if an in-tree build has previously run and subsequently cleaned.
2025-11-04 11:46:27 +13:00
YRabbit
2a3720921c
Gowin. Fix GW5A ADCs.
...
For these primitives, Gowin decided to use a different option for
describing ports—directly in the module header, i.e.
``` verilog
module ADC(input CLK);
```
instead of
``` verilog
module ADC(CLK);
input CLK;
```
Since this one-time parser becomes too confusing, it is easier to simply
add ADC descriptions as they are from a separate file, especially since
these primitives are only available in the GW5A series.
Test:
``` shell
yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a"
```
The old version of Yosys simply won't compile the design due to the lack
of port descriptions, while the new version will compile without errors.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2025-10-29 12:48:21 +10:00
Patrick Urban
14c1802b01
gatemate: fix SERDES CDR parameters
2025-10-27 15:47:48 +01:00
YRabbit
3956f103a9
Gowin. Handle the WRITE_MODE.
...
Process the WRITE_MODE in the GW5A series in a more concise manner.
You can check it in the same way as in
https://github.com/YosysHQ/yosys/pull/5440
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2025-10-25 23:15:23 +01:00
YRabbit
64700dec65
Gowin. Disable unsupported BSRAM mode in GW5A
...
All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.
Here, we prohibit the generation of BSRAM with this mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2025-10-23 09:59:56 +01:00
