github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-14 09:19:24 +00:00
Code Issues Releases Wiki Activity
1,141 Commits 130 Branches 66 Tags
398482eced4c16a22a5617246f75bbd14eaa618f
Commit Graph

1 Commits

Author SHA1 Message Date
Clifford Wolf
00a6c1d9a5 Major redesign of expr width/sign detecion (verilog/ast frontend) 2013-07-09 14:31:57 +02:00