This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-02-09 18:11:05 +00:00
Code
Issues
Releases
Wiki
Activity
13,522
Commits
119
Branches
64
Tags
3a36612ec7bbf4e445e5dc80a902002f1bd0bfa4
Commit Graph
1 Commits
Author
SHA1
Message
Date
Udi Finkelstein
80d9d15f1c
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
2018-06-05 18:00:06 +03:00