github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-26 20:23:59 +00:00
Code Issues Releases Wiki Activity
12,371 Commits 115 Branches 63 Tags
3ec00cceaa62ad7e06bdaa0fa48eaaffeae8982c
Commit Graph

3 Commits

Author SHA1 Message Date
Marcelina Kościelnicka
24027b5446 proc_memwr: Use the v2 memwr cell. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
a23d9409e7 opt_mem: Remove write ports with const-0 EN. 
Fixes #2765.
 2021-05-23 14:30:56 +02:00