github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-07 00:57:07 +00:00
Code Issues Releases Wiki Activity
15,998 Commits 119 Branches 64 Tags
474df05e8adccad063c4dbe47396b3eb9e19e1ea
Commit Graph

1 Commits

Author SHA1 Message Date
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00