github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-14 12:14:03 +00:00
Code Issues Releases Wiki Activity
5,347 Commits 124 Branches 64 Tags
4a4e28b55eb24ec4e83b092bf8478bb8149669c0
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00