github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-03 06:40:15 +00:00
Code Issues Releases Wiki Activity
9,066 Commits 134 Branches 66 Tags
4a8cecf03e5b1de409b2c8fabf4355157c5e97b5
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00