github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-04 15:17:27 +00:00
Code Issues Releases Wiki Activity
5,818 Commits 137 Branches 66 Tags
4d6fac019a9a2ca3d2f0a05eb8d08c88e04faad0
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00