github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-05 07:35:21 +00:00
Code Issues Releases Wiki Activity
4,783 Commits 137 Branches 66 Tags
4fb9ccfcd81db6d2e574bea3d142b714126d1123
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00