Emil J. Tywoniak
53585db9f7
kernel: add SwitchRule signal_src
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
a24c260998
proc_mux, genrtlil: make use of case_src for better case condition vs block tracking
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
f4a69805ae
verific: use SyncActions
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
cacd584347
proc_mux: emit fused action location src attributes on procmuxes
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
c36370f227
rtlil: add source tracking to CaseRule actions
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
7713b5a811
verilog: fix case location
2026-01-26 12:50:51 +01:00
Emil J. Tywoniak
94a53e08bc
rtlil: replace SigSig actions with new type SyncAction
2026-01-26 12:50:51 +01:00
Miodrag Milanovic
d0fa4781c6
verific: Fix -sv2017 message and formatting
2026-01-20 08:07:26 +01:00
Miodrag Milanovic
cc3038f468
verific: Fix -sv2017 message
2026-01-19 16:32:46 +01:00
Miodrag Milanovic
d095d2c405
verific: add explicit System Verilog 2017 option
2026-01-16 07:56:53 +01:00
Emil J
71feb2a2a1
Merge pull request #5604 from YosysHQ/emil/read_verilog-remove-log
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read_verilog: remove log I left behind by accident
2026-01-13 17:48:30 +00:00
Emil J. Tywoniak
83c1364eeb
read_verilog: remove log I left behind by accident
2026-01-13 18:47:23 +01:00
Emil J
5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire
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Add autowires in genblk/for expension
2026-01-13 16:40:22 +01:00
Emil J
0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz
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Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
2026-01-06 20:07:31 +01:00
N. Engelhardt
d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties
2025-12-22 16:54:43 +01:00
Robert O'Callahan
46cb05c471
Pass IdString by value instead of by const reference.
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When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
2025-12-22 01:52:59 +00:00
Robert O'Callahan
ddd6a16ee0
Add -legalize option to read_rtlil
2025-12-21 21:47:48 +00:00
N. Engelhardt
45d654e2d7
avoid merging formal properties
2025-12-17 20:25:24 +01:00
Yannick Lamarre
9814f9dc4f
Add autowires in genblk/for expension
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Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com >
2025-12-10 14:43:42 +01:00
Emil J
9871e9b17e
Merge pull request #5496 from YosysHQ/emil/liberty-flop-loops
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read_liberty: support loopy retention cells
2025-12-01 22:50:20 +01:00
Robert O'Callahan
8f0ecce53f
Forbid creating IdStrings and incrementing autoidx during multithreaded phases, and add dynamic checks for that
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We could make it safe to increment autoidx during multithreaded passes, but that's
actually undesirable because it would lead to nondeterminism. If/when we need new
IDs during parallel passes, we'll have to figure out how to allocate them in a
deterministic way, and that will depend on the details of what the pass does.
So don't try to tackle that now.
2025-11-25 21:57:46 +00:00
Mike Inouye
f098352ae6
Enable xaiger2 pass when not in NDEBUG
2025-11-21 14:23:32 -08:00
Emil J. Tywoniak
d5c1cd8fc0
read_liberty: support loopy retention cells
2025-11-20 13:21:32 +01:00
Emil J. Tywoniak
302643330c
read_liberty: add cell context to more errors, remove log_id
2025-11-20 13:21:28 +01:00
KrystalDelusion
529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params
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Handle unsized params
2025-11-12 07:14:44 +13:00
Emil J. Tywoniak
8f53d21ea7
simplify: refactor specific package import
2025-11-10 14:26:10 +01:00
Rahul Bhagwat
54e5eb1c3c
no use vector
2025-11-08 23:16:52 +05:30
Rahul Bhagwat
224109151d
add specific package imports and tests
2025-11-08 23:05:10 +05:30
Krystine Sherwin
7302bf9a66
Add CONST_FLAG_UNSIZED
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In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
2025-11-07 17:45:07 +13:00
Krystine Sherwin
a5cc905184
simplify.cc: Fix unsized const in params
2025-11-07 15:52:24 +13:00
KrystalDelusion
52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor
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Refactor getting dirs and filenames from paths to files
2025-11-05 09:12:54 +13:00
Robert O'Callahan
25aafab86b
Set port_id for Verific PortBus wires
2025-10-23 20:51:53 +00:00
Emil J
9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec
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Don't stop parsing sigspec after a {} group.
2025-10-15 17:31:11 +02:00
Robert O'Callahan
e099a7d34a
Don't stop parsing sigspec after a {} group.
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Resolves #5424
2025-10-14 21:18:58 +00:00
Emil J. Tywoniak
5cfe6a9c1e
reduce OS ifdefs, refactor getting dirs and filenames from paths to files
2025-10-14 15:46:17 +02:00
Miodrag Milanovic
1f11b2c529
verific: Add src to message missed in #5406
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
dc959cdf4a
verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
9570b39519
verifix: fix bits() deprecation warnings
2025-10-13 09:57:22 +02:00
Miodrag Milanovic
2f8f421dee
verifix: fix bits() deprecation warnings
2025-10-13 09:47:18 +02:00
Emil J
a80462f27f
Merge pull request #5339 from rocallahan/fast-rtlil-parser
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Rewrite the RTLIL parser for efficiency
2025-10-08 14:52:37 +02:00
N. Engelhardt
0b6adf832b
verific: print source location of problematic object on import error (if available)
2025-10-03 12:57:49 +02:00
Robert O'Callahan
915ad949f9
Limit the maximum size of parsed RTLIL constants to 1 Gb.
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Without this check it's trivially easy to crash Yosys with a tiny RTLIL input
by specifying a constant with very large width. Fuzz testers love hitting this
over and over again.
2025-10-01 02:17:22 +00:00
Robert O'Callahan
ac4cb5e460
Implement a handwritten recursive-descent RTLIL parser with minimal copying
2025-10-01 02:17:22 +00:00
ShinyKate
30cb72a162
Merge pull request #4125 from povik/read-blif-gate-ff
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read_blif: Represent sequential elements with gate cells
2025-09-29 08:21:16 -05:00
Jannis Harder
4bb4b6c662
verific: Extend -sva-continue-on-err to handle FSM explosion
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This also rolls back any added cells and wires, since we might have
added a lot of helper logic by the point we detect this.
2025-09-27 21:13:02 +02:00
Jannis Harder
83dd99efb7
verific: New -sva-continue-on-error import option
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This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
2025-09-24 18:58:54 +02:00
Robert O'Callahan
1e5f920dbd
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
Emil J
a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
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write_rtlil: don't sort
2025-09-22 11:14:39 +02:00
Jannis Harder
79e05a195d
verilog: Bufnorm cell backend and frontend support
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This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
Robert O'Callahan
a1141f1a4c
Remove some unnecessary .c_str() calls to the result of unescape_id()
2025-09-16 23:12:14 +00:00
