github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-15 12:36:00 +00:00
Code Issues Releases Wiki Activity
6,876 Commits 125 Branches 64 Tags
58ec1df4c26599338f2f45941ed8ca402abfe607
Commit Graph

2 Commits

Author SHA1 Message Date
Miodrag Milanovic
0de328da8f Fixed Anlogic simulation model 2019-01-25 19:25:25 +01:00
Miodrag Milanovic
83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00