Claire Wolf
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a7cc4673c3
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Fix partsel expr bit width handling and add test case
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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2020-03-08 16:12:12 +01:00 |
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Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
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Clifford Wolf
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50f22ff30c
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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Clifford Wolf
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92035fb38e
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Implemented indexed part selects
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2013-11-20 13:05:27 +01:00 |
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