github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-04 07:10:19 +00:00
Code Issues Releases Wiki Activity
6,369 Commits 134 Branches 66 Tags
5e8a98c8fd5f31b514748676804dd1237bce4225
Commit Graph

2 Commits

Author SHA1 Message Date
Miodrag Milanovic
837cb0a1b9 anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
Miodrag Milanovic
83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00