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YosysHQ.yosys
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3 Commits
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Clifford Wolf
63285b300c
Renamed temp module generated by "abc" pass from "logic" to "netlist"
2013-11-19 01:03:57 +01:00
Clifford Wolf
a694324a75
Fixed abc pass blif parser for constant bits
2013-11-13 15:46:28 +01:00
Clifford Wolf
ad9bbcbf40
Added $lut cells and abc lut mapping support
2013-07-23 16:19:34 +02:00