github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-24 19:42:18 +00:00
Code Issues Releases Wiki Activity
1,100 Commits 114 Branches 63 Tags
Commit Graph

1 Commits

Author SHA1 Message Date
Clifford Wolf
00a6c1d9a5 Major redesign of expr width/sign detecion (verilog/ast frontend) 2013-07-09 14:31:57 +02:00